Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Adders are used in processing units such as Arithmetic and Logic Units (ALUs) an essential building block, many blocks of microprocessor chips critical path, adders occupy important place. Hence reducing power, area increasing the speed significantly important. This paper proposes a modified structure Carry Skip Adder (CSKA) with reduction consumption power without affecting when compared conventional adder structures. In order to get better effectiveness CSKA by including concatenation, incrementation schemes, variable latency for proposed hybrid structure, which reduces utilized operating adder. The helps improving slack time, further voltage parallel structure. Experimental results show that 32-bit implementation has significant 42% 38.3%, 27%, 18.3% respect Conventional CI little over ahead delay. is implement 5-tap FIR filter shows area.